Interest in the rump session has proven to be quite high, with IMEC, SVTC, Intel, SEMATECH, and Tomas Palacios (from MIT) agreeing to participate.

Description of the rump session:

There have been many recent advances in the growth of III-Vs on Si based Substrates, Si-like processing of III-Vs, and heterogeneous integration of III-Vs with CMOS. As a result, we will be holding a panel discussion / rump session to discuss the future of III-V processing in Si foundries for III-V only, and III-V integration with CMOS applications. This panel will be moderated by Raytheon Senior Engineering Fellow Kamal Alavi, who will use his broad expertise to examine topics such as the following: CMOS process compatibility with III-V materials and processes, commercial applications of the technology (particularly volume drivers, how low volume defense related work can be made to fit into the Si foundry model, III-V devices vs. graphene, potential impact, and its timing, that III-V processing in Si foundries will have on traditional III-V foundries

For more information including the invited speaker list and biographical sketches, please visit our Face Book page and Twitter Feed, both of which are "ECS Sotapocs".